You mentioned your fpga runs on 112MHz sampling clock. Are you running the FPGA-Fx3 interface also on this clock?
This interface can only take a max clock of 100MHz; behaviour at higher clocks is not defined.
Does the fpga poll the dma flags for the two sockets and write into fx3 only when buffers are available?
Thanks for the questions.
We are running the interface at 100MHz. We pack two samples into every transaction, buffered by the FPGA. Yes, the FPGA uses the socket flags to determine when buffers are available. In steady state mode, the system works flawlessly. We can run for hours and hours with no dropped samples or other issues. It is ONLY on the very first cycle back to the front of the DMA buffer ring that we see this one-time hiccup. It is 100% repeatable, every time.