6 Replies Latest reply on Jan 7, 2016 8:00 PM by xchx

    packet loss in synchronous Slave FIFO mode

    mirzaii_h_1540796
              hello dear, according to "FX2LP DMB-TH TV Dongle Reference Design Guide" i made a board and every things was OK but for low frequency clocks (clear)but i needed near 27mhz clock for data input so i changed mode to synchronous Slave FIFO (Free Running MPEG CLK) and also made some little changes in firmware to support this mode ,i made some mpeg2 shape packets by a CPLD and also had a mpeg ts analyzer in the windows side to see packets,so 27mhz clock was OK and i saw mpeg2 ts packets in analyzer but until data rate near 50mbit/s .more than it i saw some packet loss near one per 1000,also it was not because of clock,also when i decrease clock to 13mhz but i see problem for data rate near 50mbit/s,so what is your idea?