I don't find in the schematics that Reset signal is associated to the VIO1 power domain. Can you please specify where exactly on the schematics do you see this?
I have attached the snap of the 'Schematics'. Please see that, the 'RESET' is connected to VIO1 bank (U1A, pin C5). But, this pin corresponds to 'CVDDQ' IO bank as per the 'Datasheet'.
FX3_Reset_VIO1_Bank.png 29.1 K