Hi, I have a design that requires an FPGA and a CPLD, each connected to the FX3. The FPGA is to be connected to the FX3 using the FIFO interface, with the FX3 as the FIFO slave. The CPLD, on the other hand, is to act as a slave to the FX3, and needs to transfer data relatively quickly, so the GPIOs are not sufficient.
This was accomplished on the FX2LP by connecting the FPGA to the Slave FIFO interface of the FX2LP and connecting the CPLD to the Address and Data lines of the FX2LP. I am looking to port this design over to the FX3, but by using the GPIF II as a Slave FIFO, I am not sure how to then hook up the CPLD as a slave device to the FX3, due to pin constraints and the fact that using the FIFO requires the GPIF.
Part of the schematic from the FX2LP version is attached for a visual aid. J3 connects to the FPGA and U7 is the CPLD.
I believe you are not going to use the FPGA and CPLD at the same time.
Can you please add a Multiplexer on your schematic to route the GPIF Data and control lines to one device (either FPGA or CPLD) at a time?