I have a design where I want to read some data from the Fx3 PPORT to an FPGA using the slave interface. I am using a 8-bit bus. I am finding that the data takes 3 clocks from setting the SLRD signal low. I read in the datasheet that it is supposed to be 2. So I am a bit confused why I am getting 3.
The extra clock cycle is when you see it from FPGA's perspective. FX3 takes only 2 clock cycles to latch the data, the one more clock cycle is required by FPGA to sample it.
- Madhu Sudhan