6 Replies Latest reply on Jan 15, 2016 2:54 AM by user_78878863

    ADC Clock and EoS

    user_365962704

      Hi all,

         

      I had been reading SAR ADC documentation, now i had read the PSoC 5LP Architecture TRM Rev *C, page 388, 38.2.3 Input Sampling section, it says the input sampling time can be programmed from 1 to 64 cycles in register SARx_CSR2[5:0] register bits, so i make a simple project where the ADC is configured to 8bit resolution, continuous sampling, i enable the EoS output and attach a digital output to it, also another to the EoC output and another one to the external clock that is feeding the ADC (1MHz clock), then i debug the component and SARx_CSR2 = 0x0440, this means the sampling time is 4 clock cycles and 8bit resolution.

         

      Later after the same section says: "The conversion time is 18 cycles for input sampling time up to four cycles.", but i see only 14 clock cycles when i plug a logic analyzer to the output, attached are two images that almost explain this. The project just configures the ADC.

         

      Any idea on why i see 14 instead of 18 clock cycles? the logic analyzer trigger is tricking me again?

         

       

         

      Thanks in advance

         

      Carlos

        • 1. Re: ADC Clock and EoS
          user_78878863

          Where do you see the 14 clock cycles? Between EOS and EOC? Or between two consecutive EOC signals?

          • 2. Re: ADC Clock and EoS
            user_365962704

            Hi, between two consecutive EoC signals.

            • 3. Re: ADC Clock and EoS
              user_78878863

              Should have looked at the pictures first ;-(

                 

              But its certainly strange - conversion time should not be lower than 16 clock cycles. Maybe you want to create a support case ('MyCases' in the top right menu) and see what Cypress has to say about it...

              • 4. Re: ADC Clock and EoS
                user_365962704

                Hi, sorry for the late reply, my application is not very critical, so i didn't keep searching why i saw that conversion time...

                   

                Just did the MyCase thing, first time i do one, so let's see how it goes, will update this post if i get responce from Cypress team.

                   

                Thanks Hli!!

                   

                Carlos

                • 5. Re: ADC Clock and EoS
                  user_365962704

                  Cypress support is quick, this is the explanation:

                     


                  The total conversion time of the SAR ADC = no of sampling clock + no of bits(resolution) + 2 clock cycle to clear the capacitor bank array.

                     

                  The conversion time changes based on the resolution of the SAR ADC and total number of sampling clock cycles. In your application, you have chosen 4 sampling clock cycles and 8 bit resolution. So the total conversion time = 4+8+2 = 14 clock cycles. That's why 14 clock cycles are appeared in the CRO.

                     

                  In the TRM, "The conversion time is 18 cycles for input sampling time up to four cycles" explains the maximum conversion time of SAR ADC for maximum resolution if the sampling time is 4 clock cycles. The maximum resolution of SAR ADC is 12 bits, so the conversion time = 4 + 12 + 2 = 18 clock cycles.

                     

                  In the TRM, it is mentioned that, " The maximum conversion time is 78 cycles for input sampling time of 64 cycles". The conversion time is derived from the above formula. The maximum resolution is 12 bits, if the sampling time is 64 cycles, the conversion time would be 64+ 12+ 2 = 78 clock cycles.
                   

                     

                  Carlos

                  • 6. Re: ADC Clock and EoS
                    user_78878863

                    Oh, then Cypress should amend the data sheet to make this more clear...

                       

                    But thanks for coming back!