3 Replies Latest reply on Jan 28, 2016 7:44 PM by user_44287455

    asynchronous clock and Datapath


      In learning to use datapaths, I created a simple 8 bit counter.  It works fine if I use a synchronized input.  If I switch to an asynchronous input, it says I need the UDB Clock Enable.  It works fine if I put one of these on the schematic and wire it up. 


      However, I really want to have the UDB Clock Enable as part of the verilog code for the 8-bit counter.  If I instantiate:


      cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
        .clock_in (CountIN),
        .enable  (1'b1),
        .clock_out (A_CountIN)


      Where CountIN is the input clock, and A_CountIN is the clock for the datapath, I get errors on build that say fixed location constraints cannot be satisfied. 


      My verilog is very rusty.... but I feel I am missing something. 


      Thanks for any advise.