This is not right forum. Please move it to PSoC5 programming or elsewhere. When re-posting, attach a project workspace bundle (use
Creator->File->Create Workspace Bundle (minimal)).
I believe to have datapath working correctly, you need to instantiate a clock sync inside the Verilog code. That's why your external sync worked. You can find example of clock sync code inside almost any Cypress component (look for *.v).
Ok, thanks. It seemed that since this was a component forum that it made sense here, but PSoC5 programming is just as good.
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I resolved it. I had verilog code which was set at the positive edge of the incoming asynchronous clock signal. However, I placed the clock sync after that code. By moving the clock sync before the positive edge checking code, and then made certain that I changed all remaining clock's to the new synchronized one, all is fine.