1) The compare and the basic counter usually works. Check the reset pulse, it will be used at the rising edge of the clock pulse See page 4 of basic counter datasheet.
2) Why don't you connect the isr directly to the DigitalComp output (set to rising edge)
1) You were right : everything worked fine once, then as the counter was not resetted it continued for one loop. I managed so the reset now is doing its job... The BasicCounter lacks of a configurable reset : synchronous or not !
2) I thought Status_Reg was mandatory to use cy_isr. I changed and connect it directly without success
No way to a have my interrupt callback entered.....
- In fact I added CyGlobalIntEnable;
And it works !
Thank you for your help
Vive la patience!
You are always welcome, Harvey.
Harvey I was looking at you last design and I found that the Clock setting of the 1.5Mhz was incorrect and the clocks page had an ! on this clock. Also the design also has a Combinational loop on net 1211. For stability you should break up the net with a a clocked LUT, that would force it to be registered and sampled. Do a search in the forum for Combinational Loop. It was in Aug 4 2015.
Thank you for taking the time to check my project, and for your comments; I was out of the office this week but I will consider your comments.