I think I figured out what my problem is. I suspect there may be a bug in how the address pins are assigned depending on the configuration chosen in the GPIF Designer tool. My intended interface was:
- 16 bit data bus
- 9 bit address bus
- 2 inputs
- 6 outputs
First of all, there is a comment in the data sheet that with a 16-bit data bus, the GPIF allows 16 configurable control pins (not sure if that includes use of the unused 16 data bits as they technically aren't control pins), so I'm not sure if there's an issue with having 17 signals + 16 data bits. The Designer tool doesn't throw an error, so I assumed it was ok.
I found that in the FX3 Programmers Manual there is a table (3-1) that shows which GPIOs are mapped to certain peripherals depending on the configuration (GPIF+UART for example). There is also another table (3-4) that shows the GPIF I/O connections for various configurations.
For my particular configuration, 35-pin 16b data, not multiplexed address, it shows the assigned pins for A[0:11]. However, according to table (3-1) it shows GPIF I/O [42:45] as NC, but that's where A[0:3] are supposed to be mapped??
I tried testing things will fewer address pins and noticed that at some point the Designer tools drops the higher number I/O and reassigns them to GPIO 29 and lower. In this case it works. This may be because once I dropped the total number of pins low enough, the Designer tool reconfigures the GPIF_BUS_CONFIG register to have the 31-pin GPIF configuration, not the 35-pin configuration, thus shifting where the address pins are mapped.
For the moment I am getting around this issue by overriding the address pins and driving them as GPIOs from the firmware. This is less than ideal, especially for anyone needing high speed communication.
Can anyone confirm this, and/or suggest a possible fix??