Unexpectedly high static timing analysis figures

[MaSo_1321201]

I've just upgraded to PSoC creator v3.3 and previously had challenges implementing designs without timing issues, however, I just compiled an old design loosely based on the UART ADC example and received some, to my mind crazy, high figures.  See the attachment, but the maximum for CyMasterClk is over 135MHz.

   

Either some amazing new fitting techniques or a bug has slipped into the software as I was expecting something around 74MHz.  Possibly a step by Cypress to reduce the speed gap with PIC32MZ and ST mcus - ignoring all the other PSoC goodness.  System operating temperature is set to 0-85°C.  Re-running the build process for industrial temperatures gives a top clock speed of 150MHz...

   

Cheers

   

Matt

[HeLi_263931]

Well, this calculation is the maximum speed that your digital logic (everything implemented in UDBs) could run at. What the actual maximum clock speed of the PSoC is doesn't really matter for that.

[MaSo_1321201]

Thank you.  I was surprised, because the maximum clock speeds were *much* lower using Creator 3.2

[HeLi_263931]

maybe the optimizer is better now. You could only ask Cypress, they should know.