4 Replies Latest reply on Mar 11, 2016 2:22 AM by dipakdaudia_1602606

    FRAM memory array....

    dipakdaudia_1602606

      Hi,

         

      I am designing a memory array of 16 or possibly 32 FRAM (SPI) devices for a battery operated datalogger for remote outdoor location. I have looked at the DC Characteristic in the datasheet for CY15B104Q (512K x 8) in particular the I/O voltage thresholds, Ioh, Iol and ILi figures. From these figures it is possible to construct an array of 32 devices. The design has individual /CS for each device so only one device is active and the rest tri-stated. My real concern is the Input capacitance that would be in the region of 6x32=192pf + board layout capacitance..Could you please comment on this. Many thanks for the help.

        • 1. Re: FRAM memory array....
          zsk

          Hi Deepak,

             

          This will not be an issue with respect to driving the I/O bus with ~200 pf load. This topology will only impact the signal rise time /fall time which inadvertently will impact the operating frequency of the setup.  

             

          For example, if the device rise time (10% to 90%) with 30 pF std test load measures 3s ns, then the rise time with ~210 pf load will be 7x of the 30 pf load, which will be 21 ns. Similarly, fall time is about 60% to 70% of the rise time of the CY15B104Q  device (depending on the drive strength of the pull up / pull down transistors). Therefore, the min SPI clock period should be calculated as 21 ns (tR) + 11 ns (tCH) + 11 ns (tCL) + 14 ns (tF) = 57 ns minimum or 17.5 MHz (max) clock. Adding min setup and hold time requirement  for the host controller input signals, the SPI clock frequency will further be reduced. 

             

          Since there is no min limit for the SPI clock frequency for CY15B104Q, as long as device specs remain within the datasheet limit, this configuration is very much doable.  Hope this clarifies. Please let me know if you have any further question.

             

          Best Regards,

             

          Shivendra

          • 2. Re: FRAM memory array....
            dipakdaudia_1602606

            Hi Shivendra

               

             Thank you for a very informative and full answer. I wasn't sure whether to assume linearly extrapolating the 30pF load figure initially when I was looking at this issue. I understand the explanation and the only thing I am not sure is the 14nS(tF) - what exactly does this represent? I am also now considering using low power Schmitt buffers on all the control lines (SI, SO and SCK) to and from the processor which is the ATmega256A3U.

            • 3. Re: FRAM memory array....
              zsk

              Hi,

                 

              tF is the signal fall time which is also impacted due to the load capacitance on the signal bus. Using Schmitt trigger input buffer is a good idea. This will eliminate any switching noise due to heavy bus load and thus avoid any false triggering. 

                 

              Please let me know if you have any further enquiry. 

                 

              Best Regards,

                 

              Shivendra

                 

              +1 (719)-321-9056; zsk@cypress.com

              • 4. Re: FRAM memory array....
                dipakdaudia_1602606

                Hi Shivendra,

                   

                 Yes that figures and makes sense. The total trace length is now 332mm on the board for the SCK and similar lengths for SI and SO (buffered by the Schmitts) and looking at these signal lines as transmission lines. I am also looking at bus termination methods. Parallel and Thevenin methods are good and simple but as my design is battery powered the AC method is looking attractive. The disadvantage is that adds additional capacitance on the bus that is already loaded and inevitably erode the rise and fall times - depending on the termination capacitor value. Reading texts on AC termination methods recommends that the minimum effective value for the capacitor is 50pF. Therefore, it looks even less likely that I will hit the original 20MHz design target.