This is an expected behaviour. If you plan to use external IFclk then the clock should be available before the FX2LP state machine is started. So if you program the slave first and the FPGA later, then this will cause a problem similar to one you are seeing.
Thank you for your reply.As you know,if I download the slave.iic to the EEPROM and download the FPGA code to the EPCS4,then I power up my board.Then how can I make sure that the slave first and the FPGA later? I have refered to the file named AN61345,but it does't work.Could you give me some advices.Thank you.
Initially configure FX2LP for internal clock in TD_INIT. After the FPGA is up, toggle a GPIO and use that signal to change the clock source from internal to external.
Thank you for you reply!
I have solved this problem as you say.