I'm using TCPWM component to drive a brdige p-mos + n-mos.
Output of component (line, line_n) is on two GPIO, configured as digital output (HW connection)
There are two situation.
1 First situation PWM generated carrier signal and signal "kill" is used for modulating signal.
2. second situation, i want to stop PWM component and put two GPIO to high impedance input (so PMOS is open and Nmos is closed, standby situation)
There are many kind of solution(use output enable with register, logic port, etc....)
Is there a best solution? via Software?
Bad condition: pmos and nmos both close.
Attached image of circuit.
Welcome in the forum, Vittorio!
The TCPWM has got the opportunity for defining a deadband to avoid both outputs high at the same moment.
The period of the PWM should stay constant while you may vary the duty cycle by changing the compare value on-the-fly.