I need the PSoC 5LP to pretend to be an asynchronous parallel ROM. The internal implementation based on "Indexed DMA" should
1) react on input pin (RD),
2) read desired address from 16 (well, actually 14) input pins (external address bus) called ADDR,
3) load it to the DMA2 source address (using DMA1 component) and
4) initiate the DMA (DMA2 component),
5) which fetches the byte from the RAM or Flash (depending on the configuration) to the output 8 pins (data bus) called DATA or control register connected to the pins (see question "d").
a) Is it possible? (I think it is)
b) Is it an issue to have data bus (8 pins) and address (16 pins) spanned across several pins in non-continuous manner? (well my data bus is at the the one physical port P3, but particular bit indexes are not mapped contiguously, e.g. my LSB data bit 0 is on pin 3 of the port P3)
c) I don't know how to do the steps 2 to 3; I followed the "Writing to Standard Registers and Components" sample from the AN84810 (PSoC®3 and PSoC 5LP Advanced DMA Topics) but I don't have the ADDR__PS register (while having DATA__PS, because of the 8 vs. 16 bit width?) which I would like to map to the DMA TD's source pointer.
d) I need to force DATA high-Z when RD pin is not high ("output enable"). Should I set the destination pointer of the DMA1 directly to DATA__PS or to an additional control register connected to the DATA pins (with output-enable wire controlled by the additional logic)? Is the output-enable wire of the output pin relevant while writing to the output pins by DMA (I read it's irrelevant while writing by CPU)?
You can implement this with nested DMA. AN84810 has an example showing how to do this.
The data pins need not be contigious. You will always read back the byte which has been written into the memory.