> Is there any way of specifying false paths or other timing exceptions for Warp synthesis in a custom component PSoC design? - None as I know. As you mentioned resolving the issue by "buffering" signals, the timing violation comes from asynchronous HDL design, so registering the outputs helps. The external pins can be synchronised or transparent, check how pin setting affects the design. There is always a last resort solution of changing system operating temperature range to 0-80 C (Design resources -> System), which would typically double Verilog code frequency limit.
Synchronizing the pins does indeed avoid the issue. Unfortunately it adds latency to the critical path which I was rather hoping to avoid. The design is configured for the narrow temperature range already I'm afraid.
Oh well, I suppose I'll have to find some other cycles to shave off somewhere else.
Honestly the main culprit is the indexed DMA which carries an unfortunate amount of latency at the moment. For one thing the safety margin for contention is set rather high since I wasn't too sure of my analysis. I should probably also try opportunistically triggering the DMA a few cycles early, then cancelling the action if it turns out not to be necessary.