You may call me "old fashioned" but I would (at least at first) try to solve that with an LUT state machine and an 8-bit bi-directional I/O port with oe signal. What might give you headache s could be the arbitration: How to handle when there is a request from both sides at the same time.
Thanks for the idea - I'll give it a bit of thought.
I must admit I was thinking of something that I could 'set and forget' so it could be used with DMA but I guess that should still be possible with a LUT.
Best approach to get a correctly working component created is to have a working project. Verilog code is not debuggable. So when you start designing that way your testing gets reduced to a go/no go test. Having something that works correctly helps to transform code (Yes! you will need some!) and resources into a working component.