3 Replies Latest reply on Apr 21, 2016 11:10 PM by user_1377889

    Parallel Port Component

    aussiesusan

      I am considering how to connect a vocoder chip to my PSOC5. The vocoder has an 8 bit parallel port and 3 control lines: a read, a write and an acknowledge line. To write to the vocoder you set the data and activate the 'write' line. When the vocoder activates the 'ack' line, it has got the value and you can deactivate the 'write' line to complete the transfer. The read process is similar in that you activate the 'read' line and wait for the vocoder to activate the 'ack' line at which time you can sample the data lines and deactivate the 'read' line.

         

      All of this can be done by the aspplicaiotn but it seems to be to be crying out for an UDB component to do all of the work.

         

      I've looked at the components I can find and it is a little like the EEPROM and external memory components but there is no need for address lines.

         

      Before I start learning how to write components for myself, I thought I'd ask if I have overlooked an existing component that would do this task or if there was a component that is close that I could look at how it was constructed to modify it for my purposes.

         

      Susan

        • 1. Re: Parallel Port Component
          user_1377889

          You may call me "old fashioned" but I would (at least at first) try to solve that with an LUT state machine and an 8-bit bi-directional I/O port with oe signal. What might give you headache s could be the arbitration: How to handle when there is a request from both sides at the same time.

             

           

             

          Bob

          • 2. Re: Parallel Port Component
            aussiesusan

            Thanks for the idea - I'll give it a bit of thought.

               

            I must admit I was thinking of something that I could 'set and forget' so it could be used with DMA but I guess that should still be possible with a LUT.

               

            Susan

            • 3. Re: Parallel Port Component
              user_1377889

              Best approach to get a correctly working component created is to have a working project. Verilog code is not debuggable. So when you start designing that way your testing gets reduced to a go/no go test. Having something that works correctly helps to transform code (Yes! you will need some!) and resources into a working component.

                 

               

                 

              Bob