Switching pins between SCB and GPIO

[Anonymous]

Hello everyone,

   

in PSoC 4100, I'm trying to use P4_0 and P4_1 as SCB pins (UART mode) for the first 3 seconds, than switch them to GPIO if no communication is received. Is there a way to do that?

I've found this article:
http://www.cypress.com/knowledge-base-article/switching-gpio-pin-connection-between-analog-and-digit...

It seems to deal with my problem but unfortunately it doesn't say how should I configure .cydwr and .cysch files. I currently have SCB component enabled and 2 more schematic pins are automatically assigned to another port during build-time.
Disabling the 2 schematic pins would force me to use SCB macros to read and write to its pins, which I suppose is not the right way to handle the problem.
Disabling SCB component obviously doesn't allow me to compile all the communication-related part.

Is anyone able to explain me how should I do this?

   

Thanks in advance

[Anonymous]

Hi,

   

You can easily do this. In topdesign use UART component and then follow these steps to reconfigure pins as a software controlled GPIOs:

   

    
1. Write to "CYREG_HSIOM_PORT_SEL4" to connect the GPIO drivers to DR register
    
2. ​Change the drive mode as required
    
3. Enable of disable the input buffer
   

   

Please refer PSoC 4 architecture and registers TRM for more details about the values to be written.

   

Thanks,

   

Rahul

[Anonymous]

Hello,

   

thank you very much for such a fast response! So the article pretty WAS the good way to do this. Only I had to:

   

#define SCB_1_RX_HSIOM_MASK   0x00000000000F
#define SCB_1_RX_HSIOM_POS    0
​
because auto-generated code only contains TX macros. Do you happen to know why?
The code now does what I wanted:

   

​// First: drive mode settings
​// (as suggested in AN86439 Table 1. Drive Modes and Applications)
SCB_1_rx_SetDriveMode(SCB_1_rx_DM_DIG_HIZ); // Hi-Z Input Pin
SCB_1_tx_SetDriveMode(SCB_1_tx_DM_STRONG); // Output Pin

// Now: set 0 to the appropriate bit locations
​// (as suggested in the linked article)
CY_SET_REG32(SCB_1_HSIOM_PORT, (CY_GET_REG32(SCB_1_HSIOM_PORT) & ~(SCB_1_RX_HSIOM_MASK)));
CY_SET_REG32(SCB_1_HSIOM_PORT, (CY_GET_REG32(SCB_1_HSIOM_PORT) & ~(SCB_1_TX_HSIOM_MASK)));

   

Sorry for bad message format

[Anonymous]

Hi,

   

Please search through the "cyfitter.h" file and you'll find both the RX/TX macros. However they might be far apart with some other macros in-between. Have a look at the macros in my project for clarity:

   

/* UART_rx */
#define UART_rx__0__DM__MASK 0x07u
#define UART_rx__0__DM__SHIFT 0
#define UART_rx__0__DR CYREG_PRT4_DR
#define UART_rx__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define UART_rx__0__HSIOM_MASK 0x0000000Fu
#define UART_rx__0__HSIOM_SHIFT 0u

   

/* Some more lines inbetween */

   

/* UART_tx */
#define UART_tx__0__DM__MASK 0x38u
#define UART_tx__0__DM__SHIFT 3
#define UART_tx__0__DR CYREG_PRT4_DR
#define UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define UART_tx__0__HSIOM_MASK 0x000000F0u
#define UART_tx__0__HSIOM_SHIFT 4u
 

[Anonymous]

Correct!
​I don't know why I didn't get the right search results though... My mistake.
Thank you very very much