I have a project that uses almost all of the PSoC 5LP UDB's. It uses multiples of a number of components.
I was needing a decent size counter but the 24-bit and 32-bit UDB counters used so much of the digital resources, but I wanted the higher counter in hardware. I had used the datapath for another part of the project and thought it might work great for that. I saw some mention in the TRM of time-multiplexing the datapath, but couldn't find any good examples. So I took a stab at a time-multiplexed datapath counter and thought I would share. For my purpose the counter did not have to run at the absolute fastest speed of the device.
It is still rough now(it seems to be working but no detailed testing yet), and I am sure there are cases where things don't work as they should, but thought I would throw it out to the community anyway. Maybe some folks will have some comments or more efficient ways to do things to make the component better. As of right now there is no documentation other than what is in this post.
Basic functionality- The down counter is a 23bit Down Counter that uses 1 8bit datapath, 1 count7(or control register) and some PLD cells. I am sure the state machine could be simplified more by someone more experienced with them and probably use less resources.
The clock should be set to 3 times the rate of the counter(so if you want 1MHz counter set clock input to 3MHz). Remember the datapath is time-multiplexed to use less resource(basically using the datapath like a simple CPU) so will not run at full clock speed.
The lowest 7 bits are set via the count7 write_period, usually default 127 is fine(because if you needed 7bit or less counter you probably wouldn't be using this component)
CY_SET_REG8(<datapath_F0_PTR>) for the middle 8 bits
CY_SET_REG8(<datapath_F1_PTR>) for the upper 8 bits
would better to eventually have a .h file that does this for you in one call.
Hope someone find it useful. Any additions are great too.