In my application we are attempting to perform quantitative capacitance measurements using the CY8C4247. I realize that this is not an application the chip was designed for and we likely will have to do our own qualification. There are a couple of major problems we are having. The following the the model we use to convert the raw counts into capacitance. It is derived from your capsense design guide. (mdac,cdac,sdiv) are parameters used for the capsense component. We are using PRS-12 to improve linearity.
def toPf(count, mdac,cdac,sdiv, t=0,cc=0,cm=0,cadc=0):
uaperbit = 1.2 * 1e-6; #1.2ua per bit
cdac = mdac * (uaperbit + t*cm);
mdac = cdac * (uaperbit + t*cc);
cmax = ((1<<16)-1)
vref = 1.2 + t * cv
fsw = 48000000.0 / (2 * sdiv) / 2; # by 2 for PRS!!!!
count += cadc*t
count = max(0,min(cmax,count))
cs = (count * mdac) / (cmax * vref * fsw) + cdac / (vref * fsw)
return cs * 1e9
The first question is, why does changing cdac/mdac result in a change in the measured capacitance value? This does not really make sense from the model.
Secondly, we are attempting to fit this model to observed data over a temperature range in order to derive the thermal coefficients. However it does not fit well. I suspect that our model is not good enough. Is there another theoretical model of capsense operation? This one does not include any term for the external Cmod capacitance which should have some effect on the measured value. Also we are using shield and I'm guessing that varying shield drive may cause issues.
Lastly, now that SP2 is out, CSX is an option for us. Is there any information available on CSX temperature effects? I could not even find a way to convert CSX measurements into capacitance values.
Any advice would be much appreciated.