How long are you transferring the data? Have you stopped transferring as soon as the buffer is filled, by monitoring the flags? If not it will result in PIB Errors getting triggered.
Please take a chipscope trace of Master signals and ensure that they are fine.
I don't understand it, should I have to stop the transfering the data to fx3 when the fifo is filled? In my case, the flag does not work.
HI I also have a problem. I just want to transfer the data that generated by FPGA to PC. But the USB CINTROL CENTER receives the wrong data . TX_data is ascending series . but RX_data as following: 7fa1 7fa2 7fa3 7fa4 7fa5 7fa6 7fa7 7fa8 7fa9 7faa 7fab 7fac 7fad 7fae 7faf 7fb0 7fb1 7fb2 7fb3 7fb4 7fb5 7fb6 7fb7 7fb8 7fb9 7fba 7fbb 7fbc 7fbd 7fbe 7fbf 7fc0 7fc1 7fc2 7fc3 7fc4 7fc5 7fc6 7fc7 7fc8 7fc9 7fca 7fcb 7fcc 7fcd 7fce 7fcf 7fd0 7fd1 7fd2 7fd3 7fd4 7fd5 7fd6 7fd7 7fd8 7fd9 7fda 7fdb 7fdc 7fdd 7fde 7fdf 7fe0 7fe1 7fe2 7fe3 7fe4 7fe5 7fe6 7fe7 7fe8 7fe9 7fea 7feb 7fec 7fed 7fee 7fef 7ff0 7ff1 7ff2 7ff3 7ff4 7ff5 7ff6 7ff7 7ff8 7ff9 7ffa 7ffb 7ffc 7ffd 7ffe 7fff c000 c001 c002 c003 c004 c005 c006 it isn't always continuous. That's why?