SpeedyCat this input is not the clock input it is for soc – Input *
This input is used for the Start of conversion or scan. It is visible if you set the Sample mode parameter to Hardware trigger. A rising edge on this input starts an ADC conversion. The first soc rising edge should be generated at least 10us after the component is started to guarantee reference and pump voltage stability. You can connect the output of a TCPWM component to this input. It can also be connected to any GPIO pin or a UDB.
This input is hidden if you set the Sample mode parameter to Free Running.
That is why you are getting an error. if you want a clock you need to select external in the clock selection on the configuration box. Also please post your code so we can check it for this error.
bobgoar, I think you misunderstood my intention. Otherwise I misunderstand the functional behaviour of ADC_SAR_Seq.
My clock shall trigger a sample each 0.001 s. Hence I need a signal to start a conversion, i.e. a signal into SOC if I configure the "sample mode" of ADC_SAR_Seq as "hardware trigger". As far as I understand, the "clock source" of ADC_SAR_Seq is a clock needed for the internal mechanics of the component (and with the setting "external" we get an input ACLK).
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You cannot use a clock component as hardware trigger. Clocks are handled differently in PSoC4s from "normal" signals. Use a FF, PWM or timer to get a working signal.
I pretty sure I connected clocks directly to ADCs in PSoC5LP, but maybe that is not possible on PSoC 4 BLE (could that be because DMA needs at least 2 SYSCLK ticks ensure triggering)?
Which one is the simplest/canonical component you would suggest? These components looks very overkill (lots of connectors).
What is a FF?
Can you post a picture of a design that triggers a ADC_SAR_Seq sample each 0.001 s using one of these suggested components, and also a picture of its component configuration? This should not be much work; I just need to know the input to ADC_SAR_Seq needed to trigger a sample. I know how to do the DMA part. I assume the EOC signal is triggered after conversion.
I need the 1000Hz clock to be as precise as possible.
It is easier for me (quite fewer work) when you post your project and give me the opportunity to apply a few changes.
Clock accuracy depends on HFCLK source. Without crystal you'll get only 2% accuracy.
FF is a flip flop. Seems to have become unusual with these highly integrated circuits we are working with ;-)
OK, thank you :) I will come back to you/this post later, because I was forced to focus on other things for the moment!
SpeedyCat, I'm waiting for you ;-))