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For clearing the interrupts the timer component already cares for. Just read the status register using Counter_ReadStatusRegister(). This will clear the bits that have caused an interrupt. See Datasheet page 14.
ahh RTFM again :)
thanks Bob ( I knew you would be fast on it) :P
I've also found something similar after some googling (know how entry for psoc3/5)
So yes automagically ReadStatusRegister() did the trick!
However, I must say this API is quite poor:
1) It is far from obvious (just the opposite) that a mutating function is called get* and also from the tech-sheet : " * Side Effects:
* Status register bits may be clear on read. " frankly maybe is the last word I look to see in tech-docs :D
2) It is quite inconsistent considering how irqs are cleared for GPIOs and TCPWM, examples I've seen so far.
Maybe I might switch to TCPWM or something similar, since I just want front/back period counts and interrupt on last/first.
It is already the 2nd time I got bitten by Counter element (before was pure GUI artefact) (in psoc-creator 3.2sp2 it is fixed)
There is a reason for the "strange" implementation: UDB.
An UDB allows to be used for nearly everything digital, though it is not an FPGA. It contains a programmable ALU, some registers, two FIFOs, a PLD area and a bunch of routable signals. You (rather: Cypress) can build an UART from it, a sophisticated counter component or a random number generator or..., or... or...
So best will be to use the fixed function based components first. When the project needs more resources use the more versatile UDB based ones.
Still at need of a component that isn't there? After a long, steep and winding learning-curve you may even create own components out of UDBs using a HDL (Hardware Description Language) named Warp Verilog. Everything already installed on your PC, including the documentation.