Many thanks! This looks really cool, and I will certainly make use of it.
Tried to import this component into my current project, but Creator failed to create the Community tab in the Component Catalog.
I'm not familiar importing components so any help would be appreciated.
To use the component add DDS24_lib dependency to the project, please follow this video for instructions:
1. Unzip DDS24_lib.zip
2. goto Project->Dependencies->Add library-> ..\DDS24_lib\DDS24_lib.cyprj. Done!
If you unzip both DDS24_lib.zip and DDS24_demos.zip in the same root folder, then all demos should recognize DDS24_lib dependency automatically, because it relies on a relative path.
Great, succeeded in importing your component.
Didn't find myself this way, but didn't go thru all the Cypress doc, my thanks for the help.
Do you plan to improve by including (all of the, or several) features you listed at the end of the datasheet?
3Lance, Features listed at the end of the datasheet are partially developed, but need testing and debugging. I decided to upload the component as-is for now.
I have modified your component and try to program it with CY8CKIT-050. In my program I wait for some iteration and changes the frequency (0-50Hz), but out freq displayed on my DMM is varying between 24-25Hz. Is there any problem with my setting.?
Project is working, thanks I get your point.
But my question is what should I do for 0Hz (When frequency output control parameter is zero)? That is why I have used DDS_Stop(). Please see attachment, it is working as per expectation.
Minimum frequency DDS can produce is Clock/2^24. If you set 0, it will oscillate at this min frequency. You can use API calls DDS_Stop / DDS_Enable, or hardware enable. Keep in mind that DDS_Stop freezes DDS output in the current state. Do not forget change control Enable settings in the Advanced tab. If you want explicitly output LOW, add some logic element after DDS.
You put wrong component on schematic (DDS24_Core). This is "invisible" sub-component which incapsulates Verilog code only (no API). Use DDS24 component as shown in the WaveDAC8 example demo provided within DDS24_demos.zip file. Also, short explanation of the WaveDAC8 project can be found in DDS24 basic applications_AN-DDS24_00_A.pdf file.
I have loaded your DDS24 library for PSoC 4 BLE used, use hardcoded method, it is workable. I wish to use a 3.0 MHz clock source for DDS24, and it divided from external crystal 24.0 MHz on PSoC 4 BLE pioneer kit, Have I any chance to implement ?
1. What about size question, http://www.cypress.com/forum/psoc-4-ble/how-can-i-handle-psoc-5-community-library-dds24-psoc-4-ble-device Have you been able to fit DDS24 and still have SW control over frequency? What is out3 in your case? DDS24 has only 2 outputs.
2. DDS24 requires input clock to operate. For high stability this clock has to be derived from XTAL in the PSoC clock distribution network. If you already have onboard 24MHz XTAL, open the Clocks subtab in Device Wide Resources panel (find it on the Project Explorer panel), and configure XTAL to be the IMO source.
P.S. The DDS-related question has been hangled in the link above.
I'm using the DDS24 component in a project. Actually I'm using two of them, and need to keep them synchronized. I use a common hw enable line and I use the load signal to program them in parallel. But if I set them to different frequencies, and then later set them to a common freq, I can't figure out how to get them synchronized, as they are at startup. I've tried DDS_Start and DDS_Init on both, but that doesn't seem to do the trick. Is there a way to re-sync them, so that the counters are identical?
p.s. I know that I can get two outputs from single DDS24, with separate phases, but I'm using that primary output for something else, and I really do need two instances.