3 Replies Latest reply on Nov 21, 2016 10:16 PM by jaroslaw.bielski_1674481

    CY7C68013A slave FIFO with external MPEGTS demod issues.

    jaroslaw.bielski_1674481

      Hi all,

         

      I am working on simple MPEGTS-USB converter using CY7C68013A and SiLabs demodulator. Currently I have implemented/working I2C proxy using EP1IN/OUT to configure demodulator, tuner etc. I have trouble with configuring Slave FIFO hardware with EP6 IN/BULK endpoint, there is no data from FIFO (timeout error from libusb library, no data while trying to read from kernel space). Could you please help me investigating what I am doing wrong?

         

      I have checked that data from demodulator are provided to CY7C68013A using Saleae Logic analyzer. If you wish I could attach screenshot from the Logic app showing the communication between demod and CY7C68013A.

         

      Please find the following HW configuration:

         
      Please find the following HW configuration:  - CY7C68013A-56LFXC (56-pin QFN package)    * SLCS#     - pulled high, configured as normal PIO (PORTACFG = 0)    * PKTEND    - VCC    * FIFOADDR1 - VCC (EP6 FIFO)    * FIFOADDR0 - GND    * SLOE      - VCC    * SLRD/RDY0 - VCC   - demodulator (http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2169-D60-short.pdf)    * parallel data bus connected to PB[0:7]    * VALID pin connected to SLWR/RDY1 (active high)
         

      Please find the following source code configuring CY7C68013A peripherals in TD_Init() function:

         
       // set the CPU clock to 48MHz  CPUCS = 0x10; SYNCDELAY;   // default to I2C bus freq = 400kHz  I2CTL |= bm400KHZ;   // Slave FIFO config, // External clock source  IFCONFIG = 0x03; SYNCDELAY;   // Disable FLAGD, SLCS pios  PORTACFG = 0x00; SYNCDELAY;   // FLAGD is configured as gpio, no signal from FIFO would be present on that pin  PINFLAGSAB = 0x00; SYNCDELAY;  PINFLAGSCD = 0x0E; SYNCDELAY; // FLAGC -> FF   // EP FIFO pin polarity (Active high SLWR (0x04))  FIFOPINPOLAR = 0x04; SYNCDELAY;   // Enable CPU features  REVCTL = 0x03;   // Order is important!  EP1OUTCFG = 0xA0; SYNCDELAY;  EP1INCFG  = 0xA0; SYNCDELAY;  EP6CFG    = 0xE0; SYNCDELAY; // BULK, IN, 512*4  EP2CFG   &= 0x7f; SYNCDELAY; // non valid  EP4CFG   &= 0x7f; SYNCDELAY; // non valid  EP8CFG   &= 0x7f; SYNCDELAY; // non valid   // The following code will restore FIFO default state (flags and bytes count)  FIFORESET = 0x80; SYNCDELAY; // set NAKALL bit to NAK all transfers from host  FIFORESET = 0x82; SYNCDELAY;  FIFORESET = 0x84; SYNCDELAY;  FIFORESET = 0x86; SYNCDELAY;  FIFORESET = 0x88; SYNCDELAY;  FIFORESET = 0x00; SYNCDELAY; // clear NAKALL bit to resume normal operation   // EP fifo config (WORDWIDE must be cleared on all FIFOs to switch PORTD to GPIO)  EP6FIFOCFG = 0x08; SYNCDELAY;// Auto IN, No zero length packets, 8bit wide  EP2FIFOCFG = 0; SYNCDELAY;  EP4FIFOCFG = 0; SYNCDELAY;  EP8FIFOCFG = 0; SYNCDELAY;   // out endpoints do not come up armed  EP1OUTBC = 0; SYNCDELAY; // arm the EP1 OUT endpoint by writing to the byte count   // Auto-commit 512-byte packets  EP6AUTOINLENH = 0x02; SYNCDELAY;  EP6AUTOINLENL = 0x00; SYNCDELAY;
         

      Best regards,
       Jaroslaw Bielski