9 Replies Latest reply on Jul 12, 2016 1:20 PM by christiab.kranz

    UDB blk_stat/bus_stat -->bus_state changes, blk_stat won't...

    user_413709686

      I want to be able to eventually do a series of UDB state machines which autofill the FIFOs and once full process, request another burst etc...

         

      I set my FIFO's appropriately (at least I think): 

         

          /***** SET UP FIFOs FOR WRITING TO *****/
          interruptState = CyEnterCriticalSection(); 
          //Clear FIFO status
          (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1);
          (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1);
          //Set FIFO levels to "At Least Half Empty" meaning bus knows two bytes can be written
          //May need to remove and set to 4 bytes depending on how the request handles...
          (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1 << 2);
          (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1 << 2);
          //Allow FIFOs to run again
          (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) &= ~(1);
          (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) &= ~(1); 
          CyExitCriticalSection(interruptState);

         

      And then inside a loop and debug mode, I write data to the FIFO's, which it takes in and I can read back the correct value from it. The "blk_stat" will assert (low to my pin) once two bytes are written, however, the bus_stat does nothing regardless of how much I write to the FIFOs, clear the FIFOs, etc... 

         

              for (i = 0; i < 4; i++){
                  CY_SET_REG8((reg8 *) rgb_control2_1_Pixel0_u0__F0_REG, test_pixel[i]);
                  j = CY_GET_REG8((reg8 *) rgb_control2_1_Pixel0_u0__F0_REG);
              }

         

      Any insights on settings I might be missing here in order to get the bus_stat to do anything other than remain high? In my datapath  I have : 

         

      .f0_bus_stat(dp0_fifo0empty),   AND .f0_blk_stat(dp0_fifo0lcl),  with both wires assigned to drive output pins for viewing...

         

      Neither signal will trigger a state transition and subsequently the instruction which moves F0->A0 and consumes the FIFOs contents.

         

      CFG15 has both F0 and F1 as BUS - should I change one? Is there something else necessary in an aux register or initialization I'm missing? I've poured over this for about two days now and am stuck.