4 Replies Latest reply on Aug 20, 2013 8:14 AM by babu.borusu

    How the Resistance are connected

    babu.borusu
              Hi Can i have picture of the resistance are connected between the memory and FPGA(memory controller). I have see the knowledge article of the memory schematic but still it is confusing me . Thanking you   
        • 1. Re: How the Resistance are connected
          prit

          Hi Subashbabu,

             

           

             

          I am sorry for the confusion. Please find the attached file with this interaction. We have updated the article and will publish on web as early as possible. The schematic in this article is from our internal characterization board. Please let us know if you have further queries.

             

           

             

          Thanks

          • 2. Re: How the Resistance are connected
            babu.borusu

             Hi Prit 

               

                      The memory is already placed on the board. How it is possible change the resistance for the output. As you said the input resistance is near to 50 ohms but problem i think with the output resistance because according to the equation for the ODT enable 35 ohms it gives and 15 ohms we have to add series to resistance.Is there any another way to change to resistance. 

               

             

               

            output resistance means where there are placed means near to memory or to FPGA. The doc which you attached is almost clear, i thank you.

            • 3. Re: How the Resistance are connected
              prit

              Hi Subashbabu,

                 

               

                 

              The series resistors (for output drivers) should be near to the memory because trace impedance and input impedance of FPGA will be 50 Ohm. So this is to make memory output impedance of 50 (35+15) Ohm.

                 

               

                 

              If the FPGA input/output and trace impedance is 50 Ohm then to match this impedance value, we need to have memory RQ = 175 Ohm, ODT pin = LOW and output drivers with 15 Ohm series resistor. This way our memory will match the input and output impedance with trace and FPGA impedance. If the trace and FPGA input/output impedance value is different value (not 50 Ohm) then we can adjust RQ value such that, it matches with the trace and FPGA impedance.

                 

               

                 

              Thanks

              • 4. Re: How the Resistance are connected
                babu.borusu
                        Hi The QDRll+ memory is working 280 Mhzs Frequency. When my termination for the input is 109 ohms and output is 36 ohms. I have taken the RQ=182 ohms(I did not add resistance in series) .