5 Replies Latest reply on Jul 12, 2016 1:13 PM by christiab.kranz

    TX DMA to Datapath FIFO to register DO/D1

    christiab.kranz

      I have build a setup using DMA to transfer data from SRAM to the FIFO F0 in an UDB datapath. If i load the FIFO to A0 all works fine, the DMA acknowledge is working, data is in A0, data is transferred via DMA.

         

      If i use "load D0 with F0" it looks like the FIFO pointers are not affected, there is no F0 bus status change. -> Therefore the DMA is not transferring the data.

         

      Capture mode ON/OFF does not change the behavior.

         

      Is this the expected behavior maybe that "load DO with F0" does not impact the FIFO read pointer? Or is there a "trick" to have "load D0 with F0" impacting the FIFO fill level?

        • 1. Re: TX DMA to Datapath FIFO to register DO/D1
          user_342122993
                  Can you post a demo project?   
          • 2. Re: TX DMA to Datapath FIFO to register DO/D1
            christiab.kranz

            Here the test project with FIFO F0 to A0. I also added a logic analyzer plot for the testcase.

               

            P0.0=clk

               

            P0.1=drq (fifo bus stat)

               

            P0.6=zc (A0==0)

               

            P0.7=nrq (fifo block stat)

               

            Looking at signal drq you can see that the datapath is fetching one byte from the FIFO at every clock cycle. The DMA is expected to deliver a 0x00,0x01,0x00,0x01... sequence out of the buffer. The signal tc gives the signal A0==0. Expected behavior is that the signal tc will toggle each clock cycles because A0 is either 0x00 or 0x01. Unfortunately that is not the case as you can see from the logic-analyzer measurement. The pulse-width is 10-12 clock cycle. No idea what is going wrong, it seem that the DMA is delivering the same value multiple times...

            • 3. Re: TX DMA to Datapath FIFO to register DO/D1
              christiab.kranz

              And here the same test project, but reading F0 to D0. This seems not to update the FIFO pointers because drq (fifo bus stat) goes to low and stays low. No data transmission

              • 4. Re: TX DMA to Datapath FIFO to register DO/D1
                christiab.kranz

                For the problem of no correct data from DMA (in the case F0->A0):

                   

                If i do the data transfer in SW, by adding a status register for reading the drq signal level, and poll this register all works well. (Putting the source code below into the endless loop.) => FIFO is working as expected, problem can only be in the DMA...

                   

                For me it looks like the DMA is sending "some" data if drq is high, but not in the correct sequence from the buffer.

                   

                uint8 i;

                   

                for (i=0; i<BUFFER_SIZE; i++)

                   

                {

                   

                  while (!TopDesign_1_StatusReg_1_Read());

                   

                  TopDesign_1_TestPath_F0_REG=txBuffer[i];

                   

                }

                • 5. Re: TX DMA to Datapath FIFO to register DO/D1
                  christiab.kranz

                  I've made some progress in debugging the DMA issue. I build a test project using an 8-bit control register mapped to an output port and a DMA writing to that register. At the output port i connected a logic-Analyzer to see the DMA transfers.

                     

                  I've set the DMA to rising edge sensitivity at the hardware request and connected a 500kHz clock to the drq input.

                     

                  The DMA was configured to CY_DMA_TD_AUTO_EXEC_NEXT, with using the same TD always.

                     

                  As you can see from the attached logic analyzer plot, the first TD is running nearly as expected, after each rising edge the DMA transfers one byte to the control-register.

                     

                  BUT starting with the second TD (in fact configured to the same TD) the DMA is not synchronized to the clock any more but transfers data with approx. 6M samples/s. All further DMA data transfers are ignoring the rising edge of the clock.

                     

                  Either there is a special not obvious setting or the DMA has a bug....

                     

                  P.S:

                     

                  I attached the test project and the logic-analyzer plot, transmitted sequence was 1,0,2,0,4,5,0,0

                     

                  P.S2:

                     

                  Also the very first byte of the DMA transmission is too short, means the second byte was transferred too fast (before the next rising edge)

                     

                  P.S3:

                     

                  Data{7:0] is the output port, P0.0 is the clock in the attached logic-analyzer plot.