1 Reply Latest reply on Jul 24, 2016 11:09 PM by JoMe_264151

    Setup time violation

    jakac_1482786

      I am getting the following warning when I compile a program for PSOC5LP

         

       

         

      Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( UART_IntClock ).

         

       

         

      I am running a UART and a USBUART at the same time.  The UARTint clock is set at 460.8 kHZ (Desired) for a 57600 baud stream.  I have it set to use the internal clock.  

         

      My USBUART is communicating with a computer (COM) and the UART is communicating with a PROC chip for Bluetooth.  I am also running an SPI line to a display.

         

      I am running PLL_out at 48 MHz.  

         

       

         

      Any reason why I'm getting this error?  The code seems to run fine, but I don't want any issues with long term stability.

         

       

         

      Best-

         

       

         

      jk

        • 1. Re: Setup time violation
          JoMe_264151

          I am able to compile a similar project without warnings, can you please post your complete project, so that we all can have a look at all of your settings. To do so, use
          Creator->File->Create Workspace Bundle (minimal)
          and attach the resulting file.

             

           

             

          Bob