I would update to PSoC Creator 3.3 CP3 (22.214.171.12404) . I would also change the while to forever instead of while(1).
Your interrupts are all at the same level I would change them as your program requires. I would also increase the Heap size from 0x080 to 0x200.
Thank you for the fast answer. Update has been made, heap size is now 200. While changes to for (;;). There is still the same problem.
Does anyone have an idea what could be.
It is more than just uncommon to use an UART the way you do. What is with start and stop bits, do they when not correct create a Tx???
When only the functionality is needed, why don't you use a shift register?
Your logic design is a bit (or Byte? ;-) complicated to follow, I would suggest to bring out to some pins the intermediate signals and check everything with a logic analyzer, a 2 channel scope wil not help you much.
Bob (another one)
PS: BTW Where in Germany are you located, I live near Bremen
Hello Bob(another one)
The signal actually looks good I have it set me on specially Pinns and studied them.The phenomenon is this, at the beginning of the communication the slave also answered correctly. But if you observed signal on the osziliskope. You can see, that the response time is always shorter until the communication collapses. With the shift register, it is a good idea, I try to be mixed as to incorporate. But in really I want use the UART, because of all the functionalities. The packages are byte-oriented.
PS: I live in the Sauerland in Menden.(Schöne Grüße aus dem verregneten Sauerland)
Did you already consider to program your own component to maintain your signals as wanted? There are some (24) UDBs within a PSoC5 chip, each consisting of some PLD area, an (programmable) ALU, a few registers, 2 FIFOs (each 4 bit deep) and a HDL programming language to define what your component shall perform.
Yes, I admit, difficult to test, easy to make errors, but lastly unbeatable (except by FPGAs).
My problem with the uart is solved. The problem lay on the internal crystal or clock generator. With a Textronic and the signal analyzer module I could identify framing errors. Unfortunately, the internal quartz is not accurate enough, so that here the error in baudrate is already more than 4%. If you still makes a bit signal synthesis, the communication breaks down. Meanwhile the communication works fine. So a tip at all, if you want to build uart data communication with PSOC, first give them an external precision quartz.