3 Replies Latest reply on Aug 11, 2016 1:11 AM by bell_1752081

    FX3 R/W problem

    bell_1752081

      I am testing R/W of FX3 with connecting to spartan6.

         

      I used a code prepared by cypress, EZ-USB FX3 SDK/1.3/firmware/slavefifo_examples/slfifosync.

         

      I attached a chipscope diagram of xilinx.

         

      I don't know why read data after data write is always zero.

         

      I want a comment what is wrong?

        • 1. Re: FX3 R/W problem
          Madhu Lakshmipathy

          Hi,

             

          I understand that you are trying to loop back the data. From the chipscope, I see that the state of the address lines are the same for both read and write. This is not possible, as same socket cannot be used as a read and write socket.

             

          In the example you mentioned, the socket with address 00 is used for slave write to FX3, and soclket with address 0x03 (i.e 11) is used for slave read.

             

          Also, for getting data from socket 3, you must have entered some data through USB Out Endpoint 0x01.

             

          Please verify these.

             

          You can refer to our AN65974 Application note for a more clear example along with the FPGA Code. It also has details of testing and demo of the project.

             

          Regards,

             

          - Madhu Sudhan

          • 2. Re: FX3 R/W problem
            bell_1752081

            Dear Sudhan, Thank for your comment.

               

            I did write successfully as sequence, FPGA write with A=00->confirm data by Transfer Data-IN on Cycontrol

               

            But I read only all zero as sequence, Transfer Data/File-OUT on Cycontrol->do FPGA read with A=11

               

            I don't know why FLAGA/B is always high when read with EPSWITCH or without?

               

            Please tell me what is wrong.

               

            best regards,

            • 3. Re: FX3 R/W problem
              bell_1752081

              Dear Sudhan,

                 

              I tried again and get a result of attached file.

                 

              FLAGA is always low during read sequence as "Transfer Data/File-OUT on Cycontrol->do FPGA read with A=11"

                 

              same result when no EPSWITCH.

                 

              What is wrong?

                 

              best regards,