2 Replies Latest reply on Aug 14, 2016 7:38 PM by zhoumiao_buaa_1617001

    GPIF pclk timing question

    zhoumiao_buaa_1617001

      The sensor:MT9M001.The output data[0:9] is valid on the falling edge of clk.

         

      FX3 GPIF setting:16bit data bus; active clock edge:negative.....

         

      When the PCLK is 27MHz, the image is normal; but when the PCLK is 48MHz,the image is sideling.

         

      The PCLK depends on the mclk of sensor.

         

      I don't konw why? there is some problem of GPIF timing?