2 Replies Latest reply on Aug 14, 2016 7:38 PM by userc_39763

    GPIF pclk timing question

      The sensor:MT9M001.The output data[0:9] is valid on the falling edge of clk.


      FX3 GPIF setting:16bit data bus; active clock edge:negative.....


      When the PCLK is 27MHz, the image is normal; but when the PCLK is 48MHz,the image is sideling.


      The PCLK depends on the mclk of sensor.


      I don't konw why? there is some problem of GPIF timing?

        • 1. Re: GPIF pclk timing question



          What is the frame rate at 48 Mhz? Can you please check if you have any buffer overflow errors? (CyU3PDmaMultiChannelCommitBuffer Api returns error).




          -Madhu Sudhan

          • 2. Re: GPIF pclk timing question

            I have checked. There is no buffer overflow errors.


            The resolution of sensor: 1280x1024. The frame rate is 30fps at 48MHz.


            I use the usbmon to monitor the amount of usb bus. The result is as follows:


            1) 27MHz: the amount of the usb bus is 2621440=1280*1024*2, it is right, the image is normal.


            2) 48MHz: the amount of the usb bus is 2623488>1280*1024*2, it is incorrect, which results in the sideling image.