There could be a timing issue between your FPGA Signals. As soon as the SLWR is asserted (made low) by the FPGA, the FPGA should start sending the data.
If there is any delay between assertion of SLWR and the point at which the FPGA starts sending data, FX3 starts sampling the data bus without any data and samples all zeros.
Please check this,
Dear Madhu Sudhan,
Attached is my waveform screenshot,Can be seen from the figure that there is almost no delay between the write signal and the data,In addition when I put the data on the port, and then send a write signal, so that the write signal lags behind the data, in the ControlCenter also want to "Bulk-in" three times.