The DMA_RDY_TH0 has a 3 clock cycle delay. So you might miss 3 clock cycles of data. Please use DMA_Wm flags instead. For details on how to set the watermark vallue, please refer the An65974 application note.
Thanks for the reply. I would definitely try that. I am just briefing the most detailed. Please comment for any other additional suggestions.
Interface Design: We are using sync_slave_fifo_2bit (Cypress supplied interface) as the reference. The Data bus width is 8-bit.
Screenshot for Interface Design:
Screen Shot of State Diagram:
Contains two sockets with socket 0 corresponding to Thread 0 and socket 1 to Thread 1. Configured two DMA channels corresponding to each socket.
1. Loads data on Thread 0 (TH0_RD_LD). When DMA (DMA_RDY_TH0) is ready the data is read into buffers using the state TH_RD.
2. On Data count hit, it enters into the next thread where loading and reading are done as explained in step 1.
3. Additionally, each read state (TH0_RD_LD and TH1_RD_LD) is associated with INTR_CPU which enters into a wait state until DMA transfer gets ready. Probably this is why we are missing the Data stream.
On verifying the continuity of Data stream it has been observed that Data stream is discontinuous as many times it enters the interrupt.
The DMA size and DMA count for Thread 0 are 16384 and 6.
The DMA size and DMA count for Thread 1 are 16384 and 16.
Also, on changing the DMA count for thread 0 it is able to build the .img file but unable to transfer data stream and exiting out with data error = -16.
We would like to verify our state diagram and also comments on choosing DMA count.
We are reading the data stream into a file and checking continuity after the entire transfer is completed. The error explained above is as follows: Ignore the interrupt for the first two times. It is due to change in USB events.
After entering into GPIF interrupt 10 times (12-2) it has been verified that the Data stream is discontinuous for 10 times as shown below
My question here:
As shown in "Download Interface_Design.png" is this possible with the FX3 without data loss?
I have also been tinkering around with a similar interface and I'm also experiencing data loss.
It would be nice if Cypress could provide some sample with 2 Hardware-Threads and explanation how this works and *without* data loss and without some special FPGA protocol logic / one clock tick should read in 8 - 16 bit, so far I haven't found anything that addresses this issue practically.
According to the samples that I have seen they all use the FX3 as clock source instead of an external FPGA.
I am able to get continuous data for 8 bit streams. Now I would like to change my firmware to support 16 bits. As described, I have changed the settings from 8 bit to 16 bit in the GPIF 2 designer and re built the code with updated gpif2_config.h settings. However I found that the streaming is being discontinuous. I thought it would be easy to port to 16 bits, but having trouble in doing so. I would be really great to find out what could be the problem. Any suggestions in this regard would be really helpful to me.
Would any Cypress engineer can answer this problem? Thanks
Indeed, it would be nice to have an answer... I'm stuck for days on this issue and no Cypress engineer helps me...