1 Reply Latest reply on Sep 10, 2016 3:38 AM by Madhu Lakshmipathy

    Other GPIFII Application for Receiver  large amounts of data problem ?

    andykung6_1652411

      We have designed a system using FX3  and  this system is two asynchronous combination with Master (FX3) and Slave (FPGA) .

         

      Slave (FPGA) is a very passive device, must Master (FX3) transmission inform reception to Slave(FPGA)  and  FPGA to be able to send data to 16Bits DataBus and let FX3 reception.

         

      As described in an uploaded image file(Image 1), we can see there are three groups of signal lines. There are sent from the Master Control pin RD, Slave reception state pin WAIT and 16Bits DataBus. Because there is no common use Master Clk, so this is a two asynchronous design concept.

         

      As shown in image file(Image 1), the expected timing diagram for the planning of the system, as shown in Figure (Image 2) to see, RD and WAIT pin initial state are keep High. When the time arrives when T2, Master requires the ability to RD Pin tie Low,in order to told the Slave side Master want to collect the data(Master must have the ability to control receive/not  receive).

         

      After RD Tie Low,Slave discovery will begin to prepare data , when the time reaches T3, Slave ready DataBus on good Data, and the WAIT tie Low told the Master can receive data on the Data Bus,When T4 after time, Master charged DataBus data  on completed, it will represent RD tie High data collection has been completed, the T5 when the time arrives,Slave discovery RD tie High, Slave will know Master has the right to receive data, and will then WAIT tie High complete the transfer once time.

         

      To start the next, Master send data will first confirm whether the High WAIT, if continue to take a High data transmission,Otherwise, wait until the Slave WAIT pin tie High.

         

      The question is, as I refer to Cypress GPIF II offer an example, most of the examples of receiving the information in the USB,Through a Slave is from the end (FPGA or others MCU) additional GPIO Pin to inform FX3, let FX3 to perform reception work,Does not seem a way to make the PC side can place an order requires the receiving FPGA information, FX3 will go in front of the execution timing of drawing 2 above.

         

      We have thought about of reference "DMA_RDY_TH1" to complete, when DMA_RDY_TH1 = true, executes the reception process (such as shown in Image 2), but this is not what we want, We hope to make the client has control over the PC, We hope to make the client has control over the PC, not observed FX35 DMA_RDY_TH1 state and then decide whether to execute the process of receiving information.

         

      therefore~

         

      Question 1: Do you have an example of what can make the PC side have mastership, when PC client requests received, FX3 able to perform drawing two receiving process described?

         

      Question 2: Do you have to help the team responsible for solving engineering problems or FAE right here in Taiwan?

         

      Thank you..