1 Reply Latest reply on Sep 13, 2016 4:58 AM by jony.star

    68103A fifo 数据传输的问题

    jony.star

      FPGA 与68013A(100PIN) 采用Slave FIFO接口,BULK传输 , 使用 EP2 OUT EP6 IN ,自动提交包方式,full speed模式,16bitBUS.异步方式(参见代码)

         

      问题一)为什么数据 在IN 方向上只有8bit的数据是正确的? 在OUT方向上也只有8bit的数据正确,而且只能正确传输奇数序列的数据。是不是贵公司的产品设计就是这样的?(数据参照如附件)?

         

      问题二)数据手册中给出的IFCLOCK 的频率是5-48Mhz,而设计指导AN63787 中给出的RD和wr的时序参考,最大频率大约是8MHZ,(实测中超过5MHZ,基本上就全部乱码了。),请问一下,slaveFIFO 接口方式,正确的最大频率应设置多少合适?

         

      哪位能解答一下,谢谢!

         

      /********************************************************************************/

         

      IFCONFIG = 0x8b;//0x0b;//0xCB; //30MHZ

         

      // we are just using the default values, yes this is not necessary...
        EP1OUTCFG = 0xA0;
        EP1INCFG = 0xA0;
        SYNCDELAY;                    // see TRM section 15.14
        EP2CFG = 0xA2;
        SYNCDELAY;                    //
        EP4CFG = 0xA0;
        SYNCDELAY;                    //
        EP6CFG = 0xE2;
        SYNCDELAY;                    //
        EP8CFG = 0XE0;

         

        EP2FIFOCFG = 0x11;SYNCDELAY;
        EP4FIFOCFG = 0x11;SYNCDELAY;
        EP6FIFOCFG = 0x09;SYNCDELAY;
        EP8FIFOCFG = 0x09;SYNCDELAY;

         

        EP6BCL = 0x80;SYNCDELAY;
        EP6BCL = 0x80;SYNCDELAY;
        EP8BCL = 0x80;SYNCDELAY;
        EP8BCL = 0x80;SYNCDELAY;
        // out endpoints do not come up armed
       
        // since the defaults are double buffered we must write dummy byte counts twice
        SYNCDELAY;                    //
        EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
        SYNCDELAY;                    //
        EP4BCL = 0x80;    
        SYNCDELAY;                    //
        EP2BCL = 0x80;                // arm EP4OUT by writing byte count w/skip.
        SYNCDELAY;                    //
        EP4BCL = 0x80;    

         


        PORTACFG =0x40;

         

        // fill up both IN endpoints

         

      //  for (i=0;i<512;i++)
      //     EP6FIFOBUF[i] = i+2;
      //  SYNCDELAY;                    //
      //  EP6BCH = 0x02;
      //  SYNCDELAY;                    //
      //  EP6BCL = 0x00;
      //
      //  for (i=0;i<512;i++)
      //     EP6FIFOBUF[i] = i+2;
      //  SYNCDELAY;                    //
      //  EP6BCH = 0x02;
      //  SYNCDELAY;                    //
      //  EP6BCL = 0x00;

         

       // myBufferCount = 0;

         

        // enable dual autopointer(s)
       // AUTOPTRSETUP |= 0x01;  

         

      }

         

      void TD_Poll(void)              // Called repeatedly while the device is idle
      {
           IFCONFIG =0x8b;// 0x0b;
                  // if EP6 IN is available, re-arm it
         if(!(EP2468STAT & bmEP6FULL))
         {
            SYNCDELAY;               
            EP6BCH = 0x02;
            SYNCDELAY;                //
            EP6BCL = 0x00;
            //memset(EP6FIFOBUF,0x00,1024);
         }
            // if there is some data in EP2 OUT, re-arm it
         if(!(EP2468STAT & bmEP2EMPTY))
         {
            SYNCDELAY;                //
            EP2BCL = 0x80;
         }

         

      /************************************************************************************/