3 Replies Latest reply on Sep 17, 2016 8:41 AM by JoMe_264151

    Hardware mux timing


      I am trying to design a circuit that oscillates at ~48 kHz using hardware muxes and clocks.  A picture is attached.  PSoC lets me build this design using 2 clocks that are synched on the two muxes.  (Master CLK is 48 MHz).  It keeps giving me a Warning 1350:Asychronous paths exist from clock2(routed) to Clock1. 




      Does anyone know why this is happening and how to resolve it?