Jianling, You haven't mention CPU clock setting. 8-bit DMA transfer takes ~14 clocs to complete, so at 48 MHz transfer rate will max out at ~3 MHz.
For 16-bit transfer take a look on FIFOin component from PSoC Sensei library:
8-bit / 16-bit FIFOin example (updated by KeerthiRocks):
Post your project to have deeper feedback.
thank you for the good point. After I changed the both pll output and master clock from 24MHz to 48MHz, the DMA seems can finish the data transfer when pixel clock is at 6MHz now. I will continue verify the memory content as next step.
Jianling, Without knowing the specifics of your code, i suspect that each second byte gets lost. Max amount of 8-bit DMA transfers achievable should be less than 48MHz / 14 = 3.4 MHz. Please let us know the results of testing.
My test confirmed that the content captured is correct at 6MHz pixel clock.
It is interesting that speed limit seems to be between 6 and 7MHz when the core clock is at 48MHz. Where did you find the information about the 14 cycles DMA transfer needs? Is it possible that DMA read and write can overlap half of their overall cycles? I am curious to this. Thanks again.
I comparing it with SRAM-DMA-VDAC transfer speed (utilized e.g. in WaveDAC), where it takes 14 clocks. My guess the difference comes from external drq trigger processing time (6 clocks for each request). I am further guessing that you have continuous inter-spoke data transfer as SRAM-to-periferial, taking 8 clocks (AN84810 - Advanced DMA topics), which makes max speed 48E+6 / 8 = 6 MHz. But why it works up to 7 MHz (7 clocks) I can't figure yet, need more learning...
Please look at the PSoC5LP TRM, part 6.2 (DMA controller).
The cycle time for a DMA transfer is 'N+6' with N=transfer count / spoke width. So it takes 7 cycles to transfer a single byte.