Welcome in the forum, Morten.
Check the schematics, so that you do not use a pin that is bypassed with a capacitor for other purposes.
I am using a pin without any external capacitors and I can see the clock coming out. The only problem is that the slew-rate is very bad.
I saw in the documentation that the PSOC4 devices has a CLK configuration for the digital output pin, but that is not available for .PSOC 5LP. Is there some other way to increase the slewrate in the current device?
Morten, WHICH pin are you using?
Can you please post your complete project, so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
How did you configure your pin? It should be set to "strong drive", and the slew rate to "fast". And you should not load the GPIO too much.
The rise time for a normal GPIO is specified as 12ns in "fast strong mode" and 60ns in "slow strong mode". The maximum frequency is 33MHz in fast mode.
The values for a SIO pin are similar, but it can sink more current.
I have attached the project as you suggested.
When I have a scope on the pin it seems the rise-time is around 60 ns. I have attached 2 clk outputs - one onto pin P0 and one to SIO P12. They both looks the same.
Morten, it is likely an issue with your scope probe. If you using $10 (for pair) probes from Ali, then 60ns slopes is what you will see on 100MHz scope. For standard probes use 10X settings on the probe and 50oHm input impedance on the scope (or add 50oHm BNC load) Alternately make your own 1:20 probe using 1k resistor at the tip of coax cable (google the recepie) and 50oHm BNC load. Using such cables I see ~5ns fronts on PSoC pins
Damn it... I just got a better scope and you are right - the rise time is around 5ns.
Thank you so much :-)