1 Reply Latest reply on Nov 7, 2016 10:32 PM by nisa

    How to connect slaveFIFO2b_fpga_top's port to FPGA?

    lee.carter


      Hi. 

      I'd like to implement slavefifo IN wih FPGA. then I've just found as below code from AN65974. 

         


      module slaveFIFO2b_fpga_top( 
      reset_in_, //input reset active low 
      clk, //input clp 27 Mhz 
      // sync, 
      fdata, 
      faddr, //output fifo address 
      slrd, //output read select 
      slwr, //output write select 
      flaga, 
      flagb, 
      flagc, 
      flagd, 
      sloe, //output output enable select 
      clk_out, //output clk 100 Mhz and 180 phase shift 
      slcs, //output chip select 
      pktend, //output pkt end 
      mode_p
      PMODE, 
      RESET, 
      // tri_state, 
      // PMODE_2 //used for debugging 
      ); 

      But I'm not sure below 1 port what should I do with that

      mode_p 

      Might be, I believe that above  1 port is connected with FX3 board. but I'm not sure and what am I supposed to with 1 port.  Even there is nowhere in the CYPRESS documents about mode_p .

      Does anyone know how to connect the mode_p  with FPGA and FX3 board?

        • 1. Re: How to connect slaveFIFO2b_fpga_top's port to FPGA?
          nisa

          The mode_p are the input signals coming to the FPGA module. These 3 bit represent the mode in which you are configuring the FPGA to driver the data. If you see the AN65974, then you will notice the mention of sw8,  these switches will select the mode for the slave fifo operation. For more details, you can refer the table provided in the application note, which shows the different supported mode.