Yes, you can combine the UDBs into larger designs. For comparision: a UDB has 2 PLDs in it, each with 4 Macrocells. So 24 UDB equal to 192 MCs - meaning a PSoC5 is a little bit larger than e.g. a XC95144. Its way smaller than a Spartan or Virtex FPGA.
thank you ANKS and hli.
Are there any restrictions on the verilog language syntax? Without considering device specific macros, does one need to re-code reuseable verilog codes in order to work with the psoc tools?
1. The Warp Verilog used in PSoC5 is very much stripped-down version of Verilog. You will not find there constructs like "initial", "signed" or "arithmetic shift", etc. Useful links which include pretty much all available resources on the subject:
Warp Verilog Reference - see attached.
2. There is a distinction between UDB datapath blocks and PLD units in PSoC. The PLD's can be programmed using Verilog language similar to FPGA. UDB datapath are modules (state machines) that are not easily programmable Verilog, but rather being glued together using the Verilog language.
As an example, attached below is a test project showing distinction between UDB and PLD modules and also demonstrating the limits of how many 24-bit DDS units can be squeezed into PSoC5. First, all available UDB's have been utilized to make 7x DDS32 using UDB datapath modules and the rest remaining PLD space was filled with 6x 24-bit DDS24 modules written entirely in Verilog (no datapath used). Maximum amount of 24-bit DDS modules that could fit into PSoC5LP is 13.
P.S. compiling project will require libraries: DDS24 and DDS32 (attached)
Thanks. it looks like the symbol generation might be my best bet for simplicity, since I don't need a highly complex design, but the existing primitives make for a cumbersome design. I will give that a try