I'm working on a Enclustra KX1 board, trying to write from the FPGA to GPIF2. Filling one buffer which according to spec should be transfered to the IN endpoint. The Cypress device is EZ-USB FX3. I do not have exact specifications of the firmware of the fx3 but it should according to their support be a bog-standard implementation of slfifosync from the SDK.
I can't quite get the interface to work, soo I was hoping I could get some help :)
I've created a simple module to write to the slaveFIFO (see StreamIN/StreamINCore).
StreamIN is a wrapper setting all the constants, and connecting some LEDS for debugging.
StreamINCore does the actual writing to the bus.
I am able to write to the FX3 and see FLAGA be asserted. I'm guessing FLAGA means there's data to read, and FLAGB means it is not full. (FLAGB=0 => Buffer=Full). ( I can write a total of 4*512 bytes to the FX3 before OUT buffer is full ).
I find the examples from Cypress hard to use, and does not seem to work for me. (See example: slfifosync.png)
Here they simply wait for FLAGB to go low as an indication of buffer being full.
In the(Designing with EZ-USB SlaveFifo) documentation this photo (write_seq.png) describes a write sequence, this is conflicting with the example. The example simply hardwires PKTEND although performing burst transfers. (Since waiting for FLAGB might go over several cycles). In my case I cannot see anything happening to FLAGB, thus it continues to write for eternity.
So how do I play the GPIF interface, or what am I doing wrong?
(SystemVerilog files are saved as *.sv.txt to be able to upload)
Thanks in advance!