1 Reply Latest reply on Nov 13, 2016 8:30 PM by gsns

    HyperRam Model Error

    stefan.steiner

      Hello together

         

      I am working with the s27kl0641 hyperRam model to validate the HyperRam controller, which I developped.

         

      I want to test the behaviour of the memory, when interacting with the memory in the BurstType Hybrid 128.

         

      At first I set the Bits of the Configuration register to CR[2:0] = 000. This is done correctly as can be seen on the ConfigReg0.png picture in the attachement. After setting the configuration register, I start a new write transasction in the memory space with the burst type wrapped burst. the start address of the memory is 0x5. So the burst should wrap at the addres 0x3F (63). one address of the transaction corresponds to 16 bit of data, where in the memory, one address corresponds to 8 bit of data. So in the memory, the wrap should occur after address 127 was written. I think, this is implemented wrong because the wrap occures already at address 63.

         

      I think, the mistake should be in the file s27kl0641.vhd somewhere at line 990.

         

      Do you agree, that this is a mistake?

         

      Thanks in advance

         

      Stefan

        • 1. Re: HyperRam Model Error
          gsns

          Hi Stefan,

             

          I believe yo have created the case for the same issue.Case No : 302201. I have contacted our Verilog/VHDL model team regarding the issue. They are looking in to it. I will update you as soon as possible.

             

          Thanks,

             

          Krishna.