2 Replies Latest reply on Nov 23, 2016 1:16 AM by userc_39405

    FPGA VHDL interface to S34ML04G1

      I'm trying to interface the above device to an FPGA, in x16 mode.  Firstly I'm confused about the address.  IF the device is 512MByte, that should be 29 address bits, but there are 30 (0-29) in the Address cycle map.  I assume this must be for the "Spare area" in each page.  But If I just want to read/write pages of 1024 words, can I ignore one address bit (set it to zero)?  My guess is that I dont use A10.


      An example of a VHDL interface would be nice!