No, any voltages on any input pins must be less than Vdd. (See the PSoC4 data sheet)
in 001-86439_AN86439_PSoC_4_-_Using_GPIO_Pins_0.pdf I see :
8 Overvoltage-Tolerant (OVT) Pins
Pins P5 and P5 in PSoC 4 BLE, Port 6 in PSoC 4 M are the OVT pins. For PSoC 4 L Port 6 and Port 8 have
OVT pins. These are similar to regular GPIOs with the following additional features:
1. Overvoltage-tolerant - There are no ESD clamp diodes at the OVT pins. In addition, the GPIO-OVT cell has the
hardware to compare the I/O supply voltage (VDDIO) and the pin voltage. If the pin voltage exceeds the VDDIO
voltage, the output driver is disabled and the pin is tristated. This results in negligible current sink at the pin. Note
that the input buffer data, during overvoltage conditions at the pin, will not be valid if the external source’s
specification of VOH and VOL do not match with the trip points of the input buffer.
What about this ?
The PSoC4 BLE and 4200M chips have a separate Vddio. Normally Vddio is the maximum voltage for all pins (and Vddio must not be higher than Vdd). The OVT pins allow a larger voltage than Vddio. But the TRM still says: "For the absolute maximum and minimum GPIO voltage, see the device datasheet." And the data sheet says that the GPIO voltage cannot be higher than Vdd (+0.5V if you really want to live on the edge).