Try Sync component instead of ClockEnable1 of 1 people found this helpful
The problem is that i want to clock the custom component only on the rising edge of the comparator output, i don't want to use extra clocks, that's why i was looking to clock the custom component with the comparator output signals.
After posting the question i attached a logic analyzer to the comparator outputs and the upper one seems really noisy (see attached image), and also found a EEVBlog video about comparators and schmitt triggers , that implementation seems interesting, i will try to do it, it uses just 1 comparator and 3 external resistors, instead of 2 comparators and 2 VDACs as my first try.
Did a quick test using the onboard switch to provide the clock (see attached project), with this i "confirmed" that any digital signal of any duty cycle can be used as clock source for UDB components, the switch is debounced so i ended up using a clock component, but the signal looks clean on the logic analyzer, so the problem on the first project seems to be the noisy signal output of the comparator, now i can follow with the datapath programming and solve noise on the comparator output later lol.
Thanks for the answer, will post any follow-ups.
without knowing all details of your measurements, instead of two comparators, can you simply amplify analog signal e.g. 100x times so it becomes fully saturated with fast transitions from 0 to 5V, becoming, almost like a "digital" signal? Then it can be additionally passed through single comparator for further conditioning.