Can you please post the project.
When using the delay, the byte to send has already moved from the FIFO to the transmit register at the time you are checking for the FIFO status. Therefore the FIFO is empty.
I think its best to use the I2S component together with the DMA. That way you don't need the CPU to handle the transfer, its done automatically.
Therefore the FIFO is empty.
That's correct. So why is the TX_FIFO_0_NOT_FULL bit stuck at 0?
Note: I am always checking this status bit in a tight loop... as I stated in the first post.
Of course I will use DMA eventually, but need to determine why this peripheral does not function as described.
You are right, I mixed this up with a FIFO_EMPTY status. Can you post a (small) project showing this behavior? Otherwise, you always create a support case with Cypress and ask them directly.