1 Reply Latest reply on Dec 16, 2016 4:13 PM by gsns

    How can I edit the test vector file for testing the verilog model?

    madeira_2102971

      Cypress provides verilog simulation model, testbench and test vector file for the SRAM CY7C1514KV18. I'd like to simulate with different values for BWS_N. How can I change the test vector file for that?

         

      Bit 3 and 2 from test vector file which are assigned to BWS_N are not used. Instead on the bus BWS_N bits 3 and 2 are assigned with bits 1 and 0 (see below).

         

       

         

          $readmemb("pksvectors.txt", lsim_vectors_qdr2);     //load input vector file
                ...
                BWSb_qdr2[3:2]=BWSb_qdr2[1:0] ;
                ...
          end
          #1 $finish; // This prevents simulation beyond end of test patterns

         

      Why is that?

         

      P.S.: CY7C1514KV18.VHD RELEASE 1.0 IS NOT WORKING CORRECTLY!!! WRITING DATA WITH BWS_N[0..3] = "1101" OR BWS_N[0..3] = "1110" FAILS!!!

         

      IF YOU HAVE MIXED-LANGUAGE SUPPORT USE THE VERILOG FUNCTIONAL MODEL REV 2.0 - NEW MODEL !

         

       

         

       

         

      Markus

        • 1. Re: How can I edit the test vector file for testing the verilog model?
          gsns

          Hi Markus,

             

          The model / device has 4 BWS inputs, since it is a x36 device.

             

          The test bench has been written to accept 2 BWS inputs, and it copies to the other two. It is a test bench, so has been optimized for execution.

             

          The test vector file can be updated by any user, to include two more bits and the test bench can be modified to accept a 4 bit string, instead of 2 bits. So you can go ahead and change the values in the test vector file as per your requirements.

             

          Thanks,

             

          Krishna.