2 Replies Latest reply on Dec 23, 2016 6:00 AM by dxin_1945386

    How to know if CX3 recongizes MIPI CSI-2 clock?

    dxin_1945386

      I'm working with a custom camera frontend that does not follow MIPI-DPHY spec exacty on the clock lane.

         

      The clock lane of this camera does not have HS-ZERO in its LP-HS transition.

         

      The clock is continuous clock mode: LP-HS transition only happen once, clock does not switch back to LP between lines or frames.

         

      Questions:

         

      1) Can CX3 recognize this non-standard clock lane? (NXP IMX6Q SoC can recognize it)

         

      2) How do I check the status of clock lane? (How do I know whether the clock is recognized by CX3 or not?)

         

          Currently I can get the camera frontend to transimit MIPI data, but I don't get the DMA callback on the CX3 side. I don't get any MIPI errors from CyU3PMipicsiGetErrors(). I'm suspecting the clock lane is not recognized by CX3. I want to confirm this. Is there a register that reports this?

         

      3) It it possible to always run the clock lane always in HS mode?

         

          For NXP IMX6Q SoC, I must reset the MIPI DPHY when the clock lane is LP, then do LP-HS transition, then the SoC will recognize MIPI clock. If I reset MIPI DPHY with the clock already in HS mode, then it won't see the clock at all.

         

          Is it also the case for CX3?