2 Replies Latest reply on Jan 3, 2017 8:36 PM by ranliang_2216111

    Bulk transfer fail on GPIF master mode

    ranliang_2216111

      Hi all

         

      we encounter bulk transfer problems with the FX3 when the DMA buffer.

         

      Background:
      We are working with the FX3 controller in master mode and are trying transfer data from the PC to FPGA in bulk transfers(8MB) using DMA.When the ready_to_transfer signal from FPGA is high the GPIF state machine DR_DATA from USB socket to the PIB socket.The DMA transfer Mode is CY_U3P_DMA_MODE_BYTE the transfer type is CY_U3P_DMA_TYPE_AUTO and the buffer is two 45kBytes.The burst length of pipeout endpoint is 15.The software works with the winusb dll and repeated WinUsb_WritePipe() on one bulk-out SS endpoint. The timeout time of Pipeout is setting to 5s.The Host Controller is Inter and ASMedia.

         

      Problem: 
      When the ready_to_transfer signal from FPGA is setting to '1' the GPIF state machine works properly and the data to the fpga is correct.But when the ready_to_transfer signal is connecting to the FPGA FIFO's valid port (which may be low when FIFO is full) the transfer is timeout everytime on Inter Host Controller PC and the ASMedia PC is fine.

         

      The transfer timeout is caused by DMA_RDY_TH2 is not available anymore when transfered 45kBytes integer times data already.
      Reduce the PIB clock frequency will also cause this problem when the ready_to_transfer signal is setting to '1'.

         

      Thougts & Questions: 
      It feels the speed of consuming DMA buffer reduced cause this problem.
      Is there anyother setting when using winusb api to write the pipe?

         

      Thank you in advance,

         

      Ran Liang