we have checked our internal database and yes the access time of Flash and SRAM access time is same as 007 and 008 models.
It is 90 ns Flash, 70 ns pSRAM/SRAM.
I was unable to find a spec sheet for the pSRAM component (SPG032D970R3R) with timing diagrams.
The device is accessed through an external memory interface (EMI) with programmable setup, wait, and hold times.
* C_SETUP field selects the setup time of the chip select assertion with respect to the write enable assertion.
* C_LENGTH selects the number of wait states inserted in any read/write cycle. The data phase of any read or write cycle will be equal to C_LENGTH +1 periods of the system clock.
* C_HOLD field selects the hold time of the chip select assertion with respect to the write enable de-assertion. The actual hold time is C_HOLD +1 periods of the system clock.
For the flash component running on a 64MHz clock (15.625ns/cycle), I figured from the timing diagrams a 2 cycle setup time + 4 cycle wait time for the external memory interface to reliably read/write the device. 0 hold.
For the pSRAM component, I figured on the same 2 cycle setup time but only 3 cycle wait. 0 hold.
Can you confirm if I read the timing correctly for the most efficient access?